The present invention relates to a gradation corrector used in correcting the gradation of a video signal in a television receiver, a video tape recorder, a video camera, a video disk or the like.
In recent years, great importance has been attached to gradation correctors in order to provide a more clear image, which is required with the increase in size of color television receivers and the improvement in image quality thereof, and more especially, in order to expand the dynamic range of an image on a CRT by passing a video signal through a non-linear amplifier to correct the gradation of the video signal.
U.S. Pat. application Ser. No. 838,844 entitled "Gradation corrector" was filed on Feb. 21, 1992 (on basis of Japanese application No. 3-32792 filed on Feb. 2, 1991). U.S. Pat. application Ser. No. 846,143 entitled "video signal gradation corrector" was filed on Mar. 5, 1992 (on basis of Japanese patent application Ser. No. 3-58657 filed on Mar. 22, 1991). A new U.S. Pat. application entitled "Gradation corrector" is filed on basis of Japanese patent application Ser. No. 3-123646 filed on May 28, 1991. These three patent applications have been assigned to the same assignee with the present application.
Explanation will now be made of the conventional gradation corrector.
FIG. 5 shows a block diagram of a gradation corrector proposed precedent to the present application. In FIG. 5, reference numeral 1 designates an A/D conversion circuit for converting an input luminance signal into a digital value. Numeral 2 designates a histogram memory for extracting a luminance histogram of the input luminance signal. In general, the luminance level is entered as an address of the memory 2 and the frequency is entered as data thereof. Numeral 3 designates a histogram operating circuit for determining the average value, the mode value, the minimum value, the maximum value, the deviation coefficient, the white area, the black area, etc. of the input luminance signal from the data of histogram memory 2 and calculates control values inclusive of a limiter level, the value of addition, a constant value of addition, an accumulation start luminance level, an accumulation stop luminance level, the maximum luminance level and so on from the determined values to output the control values to a limiter/adder circuit 5, an accumulation control register circuit 6 and a normalization control register 7. The limiter/adder circuit 5 is provided for processing the data of the histogram memory 2. Namely, on the basis of data transferred from the histogram operating circuit 3, the limiter/adder circuit 5 imposes a limitation on the frequency of the histogram so that it does not exceed a certain level and performs the operation of addition of a certain value. Generally, in a period of time when the luminance histogram is extracted (or in a period of time when the sampling is made), the data processing performed by the limiter/ adder circuit 5 is completed during a time when the address is accessed once. The accumulation start and stop levels, at which the accumulation is to be started and stopped in determining a cumulative histogram, are supplied from the histogram operating circuit 3 to the accumulation control register 6 which in turn controls a histogram accumulation adding circuit 8.
The histogram accumulation adding circuit 8 makes the accumulation of processed data from the histogram memory 2 on the basis of a control signal from the accumulation control register circuit 6. Numeral 9 designates a cumulative histogram memory for storing therein the result of accumulation by the histogram accumulation adding circuit 8. In general, the luminance level enters an address of the memory 9 and the frequency enters as data thereof. In normalizing data of the cumulative histogram to produce a look-up table, the maximum luminance level for an output luminance signal after normalization is supplied from the histogram operating circuit 3 to the normalization control register circuit 7 and the normalization control register circuit 7 controls a normalization coefficient used by a look-up table operating circuit 10 in accordance with the value of the maximum luminance level. The look-up table operating circuit 10 normalizes each data of the cumulative histogram memory 9 on the basis of an output signal of the normalization control register circuit 7. Numeral 11 designates a look-up table memory for storing therein the data normalized by the look-up table operating circuit 10. In general, the luminance level is entered as an address of the memory 11 and the frequency is entered as data thereof. Numeral 12 designates a timing control circuit 12 which makes or controls the sequence of various operations, the control for the memories, and so on. Numeral 13 designates a D/A conversion circuit by which a digital output signal corrected by use of the look-up table is converted into an analog signal.
Next, explanation will be made of the operation of the gradation corrector having the above construction. FIGS. 6A to 6F show operating waveforms of various parts.
First, an input luminance signal a is inputted to the A/D conversion circuit 1 and is converted thereby into a digital signal which is in turn outputted as a converted input luminance signal b. The converted input luminance signal b is taken as an address of the histogram memory 2 and data at that address is processed by the limiter/adder circuit 5. By performing this operation during one vertical scanning period, it is possible to extract a luminance histogram of the input luminance signal a. This situation is shown in FIG. 6A.
Next, data of the histogram memory 2 including the luminance histogram is read by the histogram operating circuit 3 which in turn calculates the average value, the mode value, the minimum value, the maximum value, the deviation coefficient, the white area, the black area, etc. of the input luminance signal a. The histogram operating circuit 3 determines control values inclusive of a limiter level, a constant value of addition, an accumulation calculation start luminance level, an accumulation calculation stop luminance level, the maximum luminance level after normalization and so on from the result of the above calculation and transfers these control signals e to the limiter/adder circuit 5, the accumulation control register circuit 6 and the normalization control register circuit 7.
Thereafter, the limiter/adder circuit 5 reads data from the histogram memory 2 to make a limiter (see FIG. 6B) and the operation of addition of a constant value (see FIG. 6C) or the like for each read data on the basis of each control signal transferred from the histogram operating circuit 3 and outputs the result to the histogram accumulation adding circuit 8 as corrected histogram data c. A curve obtained by the cumulative addition becomes closer to a linear profile as the constant value of addition is increased and approaches to a histogram flatting process as the constant value of addition is decreased (see FIG. 6D).
On the basis of the accumulation start luminance level and the accumulation stop luminance level supplied from the accumulation control register circuit 6, the histogram accumulation adding circuit 8 calculates cumulative histogram data f of the corrected histogram data c in a range between accumulation start and stop luminance levels and causes the cumulative histogram memory 9 to store the result of calculation. This situation is shown in FIGS. 6C and 6D.
Next, the look-up table operating circuit 10 reads the cumulative histogram data from the cumulative histogram memory 9 to determine a normalization coefficient so that the maximum value of the cumulative histogram data becomes the maximum output luminance level h supplied from the normalization control register circuit 7. The look-up table operating circuit 10 performs an operation on each data g of the cumulative histogram on the basis of the determined normalization coefficient and causes the look-up table memory 11 to store the result i. If the maximum output luminance level h is controlled, an operation such as an automatic contrast control (ACL) or an automatic brightness control (ABL) is possible. Such an operation is shown in FIG. 6E.
Thereafter, data in the look-up table memory 11 is read with the converted input luminance signal b being used as an address and the read data is outputted as a corrected output luminance signal j. FIG. 6F shows a histogram of the corrected output luminance signal. The D/A conversion circuit 13 outputs the corrected output luminance signal j after conversion thereof into an analog signal k.
The timing control circuit 12 controls the operations of various circuits so that the operations of the respective parts are performed at such a sequence as mentioned above. [For example, refer to Japanese Patent Application No. (Hei)1-265393, entitled "Gradation Corrector", filed on Oct. 12, 1989 (JP-A-3-126377 dated May 29, 1991)].
However, in the above construction of the precedent corrector, since the accumulation start luminance level and the accumulation stop luminance level, which are to be controlled in determining the cumulative histogram, are not controlled in accordance with an average luminance level of an input video signal, there is a first problem that by hot depending on the average luminance level of the input video signal, the gradation of the black side is destroyed, the luminance level of the black side floats or the luminance level of the white side becomes too high so that a beam current of a CRT increases, thereby causing the blooming of the CRT.
Also, the construction of the preceding corrector has a second problem that the capacity of the look-up table memory (or the number of bits required for one address) becomes large.